1. Technical Field
The present invention is directed to techniques for efficiently accessing memory, and in particular to improved techniques for efficiently accessing both aligned and unaligned data from such memory. Still more particularly, the present invention provides address and cache organization that increases the efficiency of handling unaligned data, while minimizing the physical resources needed to support it.
2. Description of Related Art
In some computer architectures, memory operand length can be defined as eight (8) bytes or less. An operand is considered aligned if it falls on an address with the least significant bit equal to a single “0” bit for a half-word (i.e. 2 bytes), the two least significant bits equal to double “00” bits for a word (4 bytes), or the three least significant bits equal to triple “000” bits for a double word (8 bytes). An operand is considered unaligned if it violates the definition of alignment. If all operands are aligned in an architecture, then only 8 bytes (the size of the cache line in such an architecture) would be required from the memory subsystem. For systems that support unaligned data, more than 8 bytes are necessary as retrieval of a single cache line will not satisfy the request. Often, unaligned data requires additional logic or circuit resources to efficiently support it.
Memory structures, like caches, provide discrete quantities of data when accessed, such discrete quantities of data sometimes being referred to as a cache line or cache block. Often, the amount of data that is provided is dictated by physical design constraints such as silicon area or wireability. The smaller the amount of data retrieved, the faster the access time for that data. Similarly, the simpler the access mechanism, the faster the access time can be. So, while complex algorithms for data retrieval are possible, they often preclude high frequency access to such data.
It would thus be desirable to provide a technique of address and cache organization that increases the efficiency of handling unaligned data, while minimizing the physical resources (transistors, wires, etc.) needed to support it.